Closing the Power Gap Between ASIC & Custom [recurso electrónico] : Tools and Techniques for Low Power Design / by David Chinnery, Kurt Keutzer.

Overview of the Factors Affecting the Power Consumption -- Pipelining to Reduce the Power -- Voltage Scaling -- Methodology to Optimize Energy of Computation for SOCs -- Linear Programming for Gate Sizing -- Linear Programming for Multi-Vth and Multi-Vdd Assignment -- Power Optimization using Multiple Supply Voltages -- Placement for Power Optimization -- Power Gating Design Automation -- Verification For Multiple Supply Voltage Designs -- Winning the Power Struggle in an Uncertain Era -- Pushing ASIC Performance in a Power Envelope -- Low Power ARM 1136JF-S Design.

This book carefully details design tools and techniques for realizing low power and energy efficiency in a highly productive design methodology. Important topics include: - Microarchitectural techniques to reduce energy per operation - Power reduction with timing slack from pipelining - Analysis of the benefits of using multiple supply and threshold voltages - Placement techniques for multiple supply voltages - Verification for multiple voltage domains - Improved algorithms for gate sizing, and assignment of supply and threshold voltages - Power gating design automation to reduce leakage - Relationships among statistical timing, power analysis, and parametric yield optimization Design examples illustrate that these techniques can improve energy efficiency by two to three times.