MARC details
| 000 -LEADER |
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04713nam a22004935i 4500 |
| 001 - CONTROL NUMBER |
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| control field |
978-0-387-28487-3 |
| 003 - CONTROL NUMBER IDENTIFIER |
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| control field |
DE-He213 |
| 005 - DATE AND TIME OF LATEST TRANSACTION |
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| control field |
20250710083942.0 |
| 007 - PHYSICAL DESCRIPTION FIXED FIELD--GENERAL INFORMATION |
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cr nn 008mamaa |
| 008 - FIXED-LENGTH DATA ELEMENTS--GENERAL INFORMATION |
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100301s2006 xxu| s |||| 0|eng d |
| 020 ## - INTERNATIONAL STANDARD BOOK NUMBER |
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| International Standard Book Number |
9780387284873 |
| -- |
99780387284873 |
| 024 7# - OTHER STANDARD IDENTIFIER |
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| Standard number or code |
10.1007/0-387-28487-7 |
| Source of number or code |
doi |
| 082 04 - DEWEY DECIMAL CLASSIFICATION NUMBER |
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| Classification number |
621.3815 |
| Edition information |
23 |
| 100 1# - MAIN ENTRY--PERSONAL NAME |
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| Personal name |
Omondi, Amos R. |
| Relator term |
editor. |
| 245 10 - TITLE STATEMENT |
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| Title |
FPGA Implementations of Neural Networks |
| Medium |
[recurso electrónico] / |
| Statement of responsibility, etc. |
edited by Amos R. Omondi, Jagath C. Rajapakse. |
| 264 #1 - PRODUCTION, PUBLICATION, DISTRIBUTION, MANUFACTURE, AND COPYRIGHT NOTICE |
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| Place of production, publication, distribution, manufacture |
Boston, MA : |
| Name of producer, publisher, distributor, manufacturer |
Springer US, |
| Date of production, publication, distribution, manufacture, or copyright notice |
2006. |
| 300 ## - PHYSICAL DESCRIPTION |
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| Extent |
XII, 360 p. |
| Other physical details |
online resource. |
| 336 ## - CONTENT TYPE |
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| Content type term |
text |
| Content type code |
txt |
| Source |
rdacontent |
| 337 ## - MEDIA TYPE |
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| Media type term |
computer |
| Media type code |
c |
| Source |
rdamedia |
| 338 ## - CARRIER TYPE |
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| Carrier type term |
recurso en línea |
| Carrier type code |
cr |
| Source |
rdacarrier |
| 347 ## - DIGITAL FILE CHARACTERISTICS |
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| File type |
text file |
| Encoding format |
PDF |
| Source |
rda |
| 505 0# - FORMATTED CONTENTS NOTE |
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| Formatted contents note |
FPGA Neurocomputers -- On the Arithmetic Precision for Implementing Back-Propagation Networks on FPGA: A Case Study -- FPNA: Concepts and Properties -- FPNA: Applications and Implementations -- Back-Propagation Algorithm Achieving 5 Gops on the Virtex-E -- FPGA Implementation of Very Large Associative Memories -- FPGA Implementations of Neocognitrons -- Self Organizing Feature Map for Color Quantization on FPGA -- Implementation of Self-Organizing Feature Maps in Reconfigurable Hardware -- FPGA Implementation of a Fully and Partially Connected MLP -- FPGA Implementation of Non-Linear Predictors -- The REMAP Reconfigurable Architecture: A Retrospective. |
| 520 ## - SUMMARY, ETC. |
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| Summary, etc. |
The development of neural networks has now reached the stage where they are employed in a large variety of practical contexts. However, to date the majority of such implementations have been in software. While it is generally recognised that hardware implementations could, through performance advantages, greatly increase the use of neural networks, to date the relatively high cost of developing Application-Specific Integrated Circuits (ASICs) has meant that only a small number of hardware neurocomputers has gone beyond the research-prototype stage. The situation has now changed dramatically: with the appearance of large, dense, highly parallel FPGA circuits it has now become possible to envisage putting large-scale neural networks in hardware, to get high performance at low costs. This in turn makes it practical to develop hardware neural-computing devices for a wide range of applications, ranging from embedded devices in high-volume/low-cost consumer electronics to large-scale stand-alone neurocomputers. Not surprisingly, therefore, research in the area has recently rapidly increased, and even sharper growth can be expected in the next decade or so. Nevertheless, the many opportunities offered by FPGAs also come with many challenges, since most of the existing body of knowledge is based on ASICs (which are not as constrained as FPGAs). These challenges range from the choice of data representation, to the implementation of specialized functions, through to the realization of massively parallel neural networks; and accompanying these are important secondary issues, such as development tools and technology transfer. All these issues are currently being investigated by a large number of researchers, who start from different bases and proceed by different methods, in such a way that there is no systematic core knowledge to start from, evaluate alternatives, validate claims, and so forth. FPGA Implementations of Neural Networks aims to be a timely one that fill this gap in three ways: First, it will contain appropriate foundational material and therefore be appropriate for advanced students or researchers new to the field. Second, it will capture the state of the art, in both depth and breadth and therefore be useful researchers currently active in the field. Third, it will cover directions for future research, i.e. embryonic areas as well as more speculative ones. |
| 650 #0 - SUBJECT ADDED ENTRY--TOPICAL TERM |
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| Topical term or geographic name entry element |
ENGINEERING. |
| 650 #0 - SUBJECT ADDED ENTRY--TOPICAL TERM |
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| Topical term or geographic name entry element |
COMPUTER SCIENCE. |
| 650 #0 - SUBJECT ADDED ENTRY--TOPICAL TERM |
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| Topical term or geographic name entry element |
SOFTWARE ENGINEERING. |
| 650 #0 - SUBJECT ADDED ENTRY--TOPICAL TERM |
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| Topical term or geographic name entry element |
ENGINEERING DESIGN. |
| 650 #0 - SUBJECT ADDED ENTRY--TOPICAL TERM |
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| Topical term or geographic name entry element |
SYSTEMS ENGINEERING. |
| 650 14 - SUBJECT ADDED ENTRY--TOPICAL TERM |
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| Topical term or geographic name entry element |
ENGINEERING. |
| 650 24 - SUBJECT ADDED ENTRY--TOPICAL TERM |
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| Topical term or geographic name entry element |
CIRCUITS AND SYSTEMS. |
| 650 24 - SUBJECT ADDED ENTRY--TOPICAL TERM |
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| Topical term or geographic name entry element |
COMPUTER SCIENCE, GENERAL. |
| 650 24 - SUBJECT ADDED ENTRY--TOPICAL TERM |
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| Topical term or geographic name entry element |
ENGINEERING DESIGN. |
| 650 24 - SUBJECT ADDED ENTRY--TOPICAL TERM |
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| Topical term or geographic name entry element |
SPECIAL PURPOSE AND APPLICATION-BASED SYSTEMS. |
| 650 24 - SUBJECT ADDED ENTRY--TOPICAL TERM |
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| Topical term or geographic name entry element |
ELECTRONIC AND COMPUTER ENGINEERING. |
| 650 24 - SUBJECT ADDED ENTRY--TOPICAL TERM |
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| Topical term or geographic name entry element |
PROCESSOR ARCHITECTURES. |
| 700 1# - ADDED ENTRY--PERSONAL NAME |
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| Personal name |
Rajapakse, Jagath C. |
| Relator term |
editor. |
| 710 2# - ADDED ENTRY--CORPORATE NAME |
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| Corporate name or jurisdiction name as entry element |
SpringerLink (Online service) |
| 773 0# - HOST ITEM ENTRY |
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| Title |
Springer eBooks |
| 776 08 - ADDITIONAL PHYSICAL FORM ENTRY |
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| Relationship information |
Printed edition: |
| International Standard Book Number |
9780387284859 |
| 856 40 - ELECTRONIC LOCATION AND ACCESS |
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| Uniform Resource Identifier |
<a href="http://dx.doi.org/10.1007/0-387-28487-7">http://dx.doi.org/10.1007/0-387-28487-7</a> |
| Public note |
Ver el texto completo en las instalaciones del CICY |
| 912 ## - |
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| -- |
ZDB-2-ENG |
| 942 ## - ADDED ENTRY ELEMENTS (KOHA) |
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| Source of classification or shelving scheme |
Dewey Decimal Classification |
| Koha item type |
Libros electrónicos |
