MARC details
| 000 -LEADER |
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| fixed length control field |
03713nam a22004815i 4500 |
| 001 - CONTROL NUMBER |
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| control field |
978-0-387-48550-8 |
| 003 - CONTROL NUMBER IDENTIFIER |
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| control field |
DE-He213 |
| 005 - DATE AND TIME OF LATEST TRANSACTION |
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| control field |
20250710084002.0 |
| 007 - PHYSICAL DESCRIPTION FIXED FIELD--GENERAL INFORMATION |
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| fixed length control field |
cr nn 008mamaa |
| 008 - FIXED-LENGTH DATA ELEMENTS--GENERAL INFORMATION |
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| fixed length control field |
100301s2007 xxu| s |||| 0|eng d |
| 020 ## - INTERNATIONAL STANDARD BOOK NUMBER |
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| International Standard Book Number |
9780387485508 |
| -- |
99780387485508 |
| 024 7# - OTHER STANDARD IDENTIFIER |
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| Standard number or code |
10.1007/0-387-48550-3 |
| Source of number or code |
doi |
| 082 04 - DEWEY DECIMAL CLASSIFICATION NUMBER |
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| Classification number |
621.3815 |
| Edition information |
23 |
| 100 1# - MAIN ENTRY--PERSONAL NAME |
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| Personal name |
Saxena, Prashant. |
| Relator term |
author. |
| 245 10 - TITLE STATEMENT |
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| Title |
Routing Congestion in VLSI Circuits: Estimation and Optimization |
| Medium |
[recurso electrónico] / |
| Statement of responsibility, etc. |
by Prashant Saxena, Rupesh S. Shelar, Sachin S. Sapatnekar. |
| 264 #1 - PRODUCTION, PUBLICATION, DISTRIBUTION, MANUFACTURE, AND COPYRIGHT NOTICE |
|---|
| Place of production, publication, distribution, manufacture |
Boston, MA : |
| Name of producer, publisher, distributor, manufacturer |
Springer US, |
| Date of production, publication, distribution, manufacture, or copyright notice |
2007. |
| 300 ## - PHYSICAL DESCRIPTION |
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| Extent |
XIV, 248 p. |
| Other physical details |
online resource. |
| 336 ## - CONTENT TYPE |
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| Content type term |
text |
| Content type code |
txt |
| Source |
rdacontent |
| 337 ## - MEDIA TYPE |
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| Media type term |
computer |
| Media type code |
c |
| Source |
rdamedia |
| 338 ## - CARRIER TYPE |
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| Carrier type term |
recurso en línea |
| Carrier type code |
cr |
| Source |
rdacarrier |
| 347 ## - DIGITAL FILE CHARACTERISTICS |
|---|
| File type |
text file |
| Encoding format |
PDF |
| Source |
rda |
| 490 1# - SERIES STATEMENT |
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| Series statement |
Series on Integrated Circuits and Systems, |
| International Standard Serial Number |
1558-9412 |
| 505 0# - FORMATTED CONTENTS NOTE |
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| Formatted contents note |
The Origins of Congestion -- An Introduction to Routing Congestion -- The Estimation of Congestion -- Placement-level Metrics for Routing Congestion -- Synthesis-level Metrics for Routing Congestion -- The Optimization of Congestion -- Congestion Optimization During Interconnect Synthesis and Routing -- Congestion Optimization During Placement -- Congestion Optimization During Technology Mapping and Logic Synthesis -- Congestion Implications of High Level Design. |
| 520 ## - SUMMARY, ETC. |
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| Summary, etc. |
With the dramatic increases in on-chip packing densities, routing congestion has become a major problem in chip design. The problem is especially acute as interconnects are also the performance bottleneck in integrated circuits. The solution lies in judicious resource management. This involves intelligent allocation of the available interconnect resources, up-front planning of the wire routes for even wire distributions, and transformations that make the physical synthesis flow congestion-aware. Routing Congestion in VLSI Circuits: Estimation and Optimization provides the reader with a complete understanding of the root causes of routing congestion in present-day and future VLSI circuits, available techniques for estimating and optimizing this congestion, and a critical analysis of the accuracy and effectiveness of these techniques, so that the reader may prudently choose an approach that is appropriate to their design goals. The scope of the work includes metrics and optimization techniques for routing congestion at various stages of the VLSI design flow, including the architectural level, the logic synthesis/technology mapping level, the placement phase, and the routing step. A particular focus of this work is on the congestion issues that deal primarily with standard cell based design. Routing Congestion in VLSI Circuits: Estimation and Optimization is a valuable reference for CAD developers and researchers, design methodology engineers, VLSI design and CAD students, and VLSI design engineers. |
| 650 #0 - SUBJECT ADDED ENTRY--TOPICAL TERM |
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| Topical term or geographic name entry element |
ENGINEERING. |
| 650 #0 - SUBJECT ADDED ENTRY--TOPICAL TERM |
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| Topical term or geographic name entry element |
COMPUTER AIDED DESIGN. |
| 650 #0 - SUBJECT ADDED ENTRY--TOPICAL TERM |
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| Topical term or geographic name entry element |
TELECOMMUNICATION. |
| 650 #0 - SUBJECT ADDED ENTRY--TOPICAL TERM |
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| Topical term or geographic name entry element |
SYSTEMS ENGINEERING. |
| 650 14 - SUBJECT ADDED ENTRY--TOPICAL TERM |
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| Topical term or geographic name entry element |
ENGINEERING. |
| 650 24 - SUBJECT ADDED ENTRY--TOPICAL TERM |
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| Topical term or geographic name entry element |
CIRCUITS AND SYSTEMS. |
| 650 24 - SUBJECT ADDED ENTRY--TOPICAL TERM |
|---|
| Topical term or geographic name entry element |
COMPUTER-AIDED ENGINEERING (CAD, CAE) AND DESIGN. |
| 650 24 - SUBJECT ADDED ENTRY--TOPICAL TERM |
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| Topical term or geographic name entry element |
COMMUNICATIONS ENGINEERING, NETWORKS. |
| 700 1# - ADDED ENTRY--PERSONAL NAME |
|---|
| Personal name |
Shelar, Rupesh S. |
| Relator term |
author. |
| 700 1# - ADDED ENTRY--PERSONAL NAME |
|---|
| Personal name |
Sapatnekar, Sachin S. |
| Relator term |
author. |
| 710 2# - ADDED ENTRY--CORPORATE NAME |
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| Corporate name or jurisdiction name as entry element |
SpringerLink (Online service) |
| 773 0# - HOST ITEM ENTRY |
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| Title |
Springer eBooks |
| 776 08 - ADDITIONAL PHYSICAL FORM ENTRY |
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| Relationship information |
Printed edition: |
| International Standard Book Number |
9780387300375 |
| 830 #0 - SERIES ADDED ENTRY--UNIFORM TITLE |
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| Uniform title |
Series on Integrated Circuits and Systems, |
| International Standard Serial Number |
1558-9412 |
| 856 40 - ELECTRONIC LOCATION AND ACCESS |
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| Uniform Resource Identifier |
<a href="http://dx.doi.org/10.1007/0-387-48550-3">http://dx.doi.org/10.1007/0-387-48550-3</a> |
| Public note |
Ver el texto completo en las instalaciones del CICY |
| 912 ## - |
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| -- |
ZDB-2-ENG |
| 942 ## - ADDED ENTRY ELEMENTS (KOHA) |
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| Source of classification or shelving scheme |
Dewey Decimal Classification |
| Koha item type |
Libros electrónicos |
