Design, Automation, and Test in Europe (Record no. 61738)

MARC details
000 -LEADER
fixed length control field 05379nam a22004815i 4500
001 - CONTROL NUMBER
control field 978-1-4020-6488-3
003 - CONTROL NUMBER IDENTIFIER
control field DE-He213
005 - DATE AND TIME OF LATEST TRANSACTION
control field 20251006084534.0
007 - PHYSICAL DESCRIPTION FIXED FIELD--GENERAL INFORMATION
fixed length control field cr nn 008mamaa
008 - FIXED-LENGTH DATA ELEMENTS--GENERAL INFORMATION
fixed length control field 100301s2008 ne | s |||| 0|eng d
020 ## - INTERNATIONAL STANDARD BOOK NUMBER
International Standard Book Number 9781402064883
020 ## - INTERNATIONAL STANDARD BOOK NUMBER
International Standard Book Number 99781402064883
024 7# - OTHER STANDARD IDENTIFIER
Standard number or code 10.1007/978-1-4020-6488-3
Source of number or code doi
082 04 - DEWEY DECIMAL CLASSIFICATION NUMBER
Classification number 621.3815
Edition information 23
100 1# - MAIN ENTRY--PERSONAL NAME
Personal name Lauwereins, Rudy.
Relator term editor.
245 10 - TITLE STATEMENT
Title Design, Automation, and Test in Europe
Medium [electronic resource] :
Remainder of title The Most Influential Papers of 10 Years Date /
Statement of responsibility, etc. edited by Rudy Lauwereins, Jan Madsen.
264 #1 - PRODUCTION, PUBLICATION, DISTRIBUTION, MANUFACTURE, AND COPYRIGHT NOTICE
Place of production, publication, distribution, manufacture Dordrecht :
Name of producer, publisher, distributor, manufacturer Springer Netherlands,
Date of production, publication, distribution, manufacture, or copyright notice 2008.
300 ## - PHYSICAL DESCRIPTION
Other physical details online resource.
336 ## - CONTENT TYPE
Content type term text
Content type code txt
Source rdacontent
337 ## - MEDIA TYPE
Media type term computer
Media type code c
Source rdamedia
338 ## - CARRIER TYPE
Carrier type term online resource
Carrier type code cr
Source rdacarrier
347 ## - DIGITAL FILE CHARACTERISTICS
File type text file
Encoding format PDF
Source rda
505 0# - FORMATTED CONTENTS NOTE
Formatted contents note System Level Design -- System Level Design: Past, Present, and Future -- Scheduling of Conditional Process Graphs for the Synthesis of Embedded Systems -- EXPRESSION: A Language for Architecture Exploration Through Compiler/Simulator Retargetability -- RTOS Modeling for System Level Design -- Context-Aware Performance Analysis for Efficient Embedded System Design -- Lock-Free Synchronization for Dynamic Embedded Real-Time Systems -- What If You Could Design Tomorrow's System Today? -- Networks on Chip -- Networks on Chips -- A Generic Architecture for On-Chip Packet-Switched Interconnections -- Trade-offs in the Design of a Router with Both Guaranteed and Best-Effort Services for Networks on Chip -- Exploiting the Routing Flexibility for Energy/Performance-Aware Mapping of Regular NoC Architectures -- xpipesCompiler: A Tool for Instantiating Application-Specific Networks on Chip -- A Network Traffic Generator Model for Fast Network-on-Chip Simulation -- Modeling, Simulation and Run-Time Management -- Modeling, Simulation and Run-Time Management -- Dynamic Power Management for Nonstationary Service Requests -- Quantitative Comparison of Power Management Algorithms -- Energy Efficiency of the IEEE 802.15.4 Standard in Dense Wireless Microsensor Networks: Modeling and Improvement Perspectives -- Statistical Blockade: A Novel Method for Very Fast Monte Carlo Simulation of Rare Circuit Events, and its Application -- Compositional Specification of Behavioral Semantics -- Design Technology for Advanced Digital Systems in CMOS and Beyond -- Design Technology for Advanced Digital Systems in CMOS and Beyond -- Address Bus Encoding Techniques for System-Level Power Optimization -- MOCSYN: Multiobjective Core-Based Single-Chip System Synthesis -- Minimum Energy Fixed-Priority Scheduling for Variable Voltage Processors -- Synthesis and Optimization of Threshold Logic Networks with Application to Nanotechnologies -- Physical Design and Validation -- Physical Design and Validation -- Interconnect Tuning Strategies for High-Performance ICs -- Efficient Inductance Extraction via Windowing -- Soft-Error Tolerance Analysis and Optimization of Nanometer Circuits -- A Single Photon Avalanche Diode Array Fabricated in Deep-Submicron CMOS Technology -- Test and Verification -- The Test and Verification Influential Papers in the 10 Years of DATE -- Cost Reduction and Evaluation of a Temporary Faults-Detecting Technique -- An Integrated System-on-Chip Test Framework -- Efficient Spectral Techniques for Sequential ATPG -- BerkMin: A Fast and Robust Sat-Solver -- Improving Compression Ratio, Area Overhead, and Test Application Time for System-on-Chip Test Data Compression/Decompression -- An Effective Technique for Minimizing the Cost of Processor Software-Based Diagnosis in SoCs.
520 ## - SUMMARY, ETC.
Summary, etc. The Design, Automation and Test in Europe (DATE) conference celebrated in 2007 its tenth anniversary. As a tribute to the chip and system-level design and design technology community, this book presents a compilation of the three most influential papers of each year. This provides an excellent historical overview of the evolution of a domain that contributed substantially to the growth and competitiveness of the circuit electronics and systems industry. The papers were grouped in six sections: System Level Design; Networks on Chip; Modeling, Simulation and Run-Time Management; Digital Systems in CMOS and Beyond; Physical Design and Validation; and Test and Verification. The winners of the prestigious EDAA Lifetime Achievement Award as well as other recognized experts in their field wrote an introduction to each section, summarizing the history in their domain and indicating how the selected DATE papers contributed to it.
650 #0 - SUBJECT ADDED ENTRY--TOPICAL TERM
Topical term or geographic name entry element ENGINEERING.
650 #0 - SUBJECT ADDED ENTRY--TOPICAL TERM
Topical term or geographic name entry element COMPUTER HARDWARE.
650 #0 - SUBJECT ADDED ENTRY--TOPICAL TERM
Topical term or geographic name entry element COMPUTER NETWORK ARCHITECTURES.
650 #0 - SUBJECT ADDED ENTRY--TOPICAL TERM
Topical term or geographic name entry element ELECTRONICS.
650 #0 - SUBJECT ADDED ENTRY--TOPICAL TERM
Topical term or geographic name entry element SYSTEMS ENGINEERING.
650 14 - SUBJECT ADDED ENTRY--TOPICAL TERM
Topical term or geographic name entry element ENGINEERING.
650 24 - SUBJECT ADDED ENTRY--TOPICAL TERM
Topical term or geographic name entry element CIRCUITS AND SYSTEMS.
650 24 - SUBJECT ADDED ENTRY--TOPICAL TERM
Topical term or geographic name entry element ELECTRONICS AND MICROELECTRONICS, INSTRUMENTATION.
650 24 - SUBJECT ADDED ENTRY--TOPICAL TERM
Topical term or geographic name entry element COMPUTER HARDWARE.
650 24 - SUBJECT ADDED ENTRY--TOPICAL TERM
Topical term or geographic name entry element COMPUTER SYSTEMS ORGANIZATION AND COMMUNICATION NETWORKS.
700 1# - ADDED ENTRY--PERSONAL NAME
Personal name Madsen, Jan.
Relator term editor.
710 2# - ADDED ENTRY--CORPORATE NAME
Corporate name or jurisdiction name as entry element SpringerLink (Online service)
773 0# - HOST ITEM ENTRY
Title Springer eBooks
776 08 - ADDITIONAL PHYSICAL FORM ENTRY
Relationship information Printed edition:
International Standard Book Number 9781402064876
856 40 - ELECTRONIC LOCATION AND ACCESS
Uniform Resource Identifier <a href="http://dx.doi.org/10.1007/978-1-4020-6488-3">http://dx.doi.org/10.1007/978-1-4020-6488-3</a>
Public note Ver el texto completo en las instalaciones del CICY
912 ## -
-- ZDB-2-ENG
942 ## - ADDED ENTRY ELEMENTS (KOHA)
Source of classification or shelving scheme Dewey Decimal Classification
Koha item type Libros electrónicos
Holdings
Lost status Source of classification or shelving scheme Damaged status Not for loan Collection Home library Current library Shelving location Date acquired Total checkouts Full call number Date last seen Price effective from Koha item type
  Dewey Decimal Classification     Libro electrónico CICY CICY Libro electrónico 06.10.2025   621.3815 06.10.2025 06.10.2025 Libros electrónicos