Rapid Prototyping of Digital Systems [recurso electrónico] / by James O. Hamblen, Tyson S. Hall, Michael D. Furman.

Tutorial I: The 15-Minute Design -- The Altera UP 3 Board -- Programmable Logic Technology -- Tutorial II: Sequential Design and Hierarchy -- UP3core Library Functions -- Using VHDL for Synthesis of Digital Hardware -- Using Verilog for Synthesis of Digital Hardware -- State Machine Design: The Electric Train Controller -- A Simple Computer Design: The µP 3 -- VGA Video Display Generation -- Interfacing to the PS/2 Keyboard and Mouse -- Legacy Digital I/O Interfacing Standards -- UP 3 Robotics Projects -- A RISC Design: Synthesis of the MIPS Processor Core -- Introducing System-on-a-Programmable-Chip -- Tutorial III: Nios II Processor Software Development -- Tutorial IV: Nios II Processor Hardware Design.

Rapid Prototyping of Digital Systems: Quartus II Edition provides an exciting and challenging laboratory component for undergraduate digital logic and computer design courses using FPGAs and CAD tools for simulation and hardware implementation. The more advanced topics and exercises also make this text useful for upper level courses in digital logic, programmable logic, and embedded systems. This new version of the widely used Rapid Prototyping of Digital Systems, Second Edition, now uses Altera's new Quartus II CAD tool and includes laboratory projects for Altera's UP 2 and the new UP 3 FPGA board. Rapid Prototyping of Digital Systems: Quartus II Edition includes four tutorials on the Altera Quartus II and NIOS II tool environment, an overview of programmable logic, and IP cores with several easy-to-use input and output functions. These features were developed to help students get started quickly. Early design examples use schematic capture and IP cores developed for the Altera UP FPGA boards. VHDL is used for more complex designs after a short introduction to VHDL-based synthesis. New to this edition is an overview of System-on-a-Programmable Chip (SOPC) technology and SOPC design examples for the UP3 using Altera's new NIOS II Processor hardware and C software development tools.