TY  - BOOK
AU  - Tan,Chuan Seng
AU  - Gutmann,Ronald J.
AU  - Reif,L.Rafael
ED  - SpringerLink (Online service)
TI  - Wafer Level 3-D ICs Process Technology
T2  - Integrated Circuits and Systems,
SN  - 9780387765341
PY  - 2008///
CY  - Boston, MA
PB  - Springer US
KW  - ENGINEERING
KW  - ELECTRONICS
KW  - OPTICAL MATERIALS
KW  - SURFACES (PHYSICS)
KW  - ELECTRONICS AND MICROELECTRONICS, INSTRUMENTATION
KW  - OPTICAL AND ELECTRONIC MATERIALS
KW  - SURFACES AND INTERFACES, THIN FILMS
KW  - ENGINEERING, GENERAL
N1  - Overview of Wafer-Level 3D ICs -- Monolithic 3D Integrated Circuits -- Stacked CMOS Technologies -- Wafer-Bonding Technologies and Strategies for 3D ICs -- Through-Silicon Via Fabrication, Backgrind, and Handle Wafer Technologies -- Cu Wafer Bonding for 3D IC Applications -- Cu/Sn Solid-Liquid Interdiffusion Bonding -- An SOI-Based 3D Circuit Integration Technology -- 3D Fabrication Options for High-Performance CMOS Technology -- 3D Integration Based upon Dielectric Adhesive Bonding -- Direct Hybrid Bonding -- 3D Memory -- Circuit Architectures for 3D Integration -- Thermal Challenges of 3D ICs -- Status and Outlook
N2  - Wafer Level 3-D ICs Process Technology focuses on foundry-based process technology that enables the fabrication of 3-D ICs. The core of the book discusses alternative technology platforms for pre-packaging wafer level 3-D ICs, with an emphasis on wafer-to-wafer stacking. Driven by the need for improved performance, a number of companies, consortia and universities are researching methods to use short, monolithically-fabricated, vertical interconnections to replace the long interconnects found in 2-D ICs. Stacking disparate technologies to provide various combinations of densely-packed functions, such as logic, memory, MEMS, displays, RF, mixed-signal, sensors, and power delivery is potentially possible with 3-D heterogeneous integration, making this technology the "Holy Grail" of system integration. Wafer Level 3-D ICs Process Technology is an edited book based on chapters contributed by various experts in the fields of wafer-level 3-D ICs process technology and applications enabled by 3-D integration
UR  - http://dx.doi.org/10.1007/978-0-387-76534-1
ER  -