TY  - BOOK
AU  - Kogel,Tim
AU  - Leupers,Rainer
AU  - Meyr,Heinrich
ED  - SpringerLink (Online service)
TI  - Integrated System-Level Modeling of Network-on-Chip enabled Multi-Processor Platforms
SN  - 9781402048265
U1  - 621.3815 23
PY  - 2006///
CY  - Dordrecht
PB  - Springer Netherlands
KW  - ENGINEERING
KW  - SOFTWARE ENGINEERING
KW  - COMPUTER SIMULATION
KW  - COMPUTER AIDED DESIGN
KW  - ELECTRONICS
KW  - SYSTEMS ENGINEERING
KW  - CIRCUITS AND SYSTEMS
KW  - ELECTRONICS AND MICROELECTRONICS, INSTRUMENTATION
KW  - SIMULATION AND MODELING
KW  - SOFTWARE ENGINEERING/PROGRAMMING AND OPERATING SYSTEMS
KW  - SPECIAL PURPOSE AND APPLICATION-BASED SYSTEMS
KW  - COMPUTER-AIDED ENGINEERING (CAD, CAE) AND DESIGN
N1  - Foreword. Preface -- 1. Introduction -- 2. Embedded SOC Applications -- 3. Classification of Platform Elements -- 4. System Level Design Principles -- 5. Related Work -- 6. Methodology Overview -- 7. Unified Timing Model -- 8. MP-SOC Simulation Framework -- 9. Case Study -- 10. Summary -- Appendices. A: The OSCI TLM Standard. B: The OCPIP TL3 Channel. C: The Architects View Framework -- List of Figures. List of Tables. References -- Index
N2  - The drastic performance, flexibility and energy-efficiency requirements of embedded applications drive the System-on-Chip integration towards heterogeneous multiprocessor platforms. Electronic System Level (ESL) design methodologies and tools have emerged to tackle the challenges of such complex SoC designs prior to RTL and silicon availability. In particular SystemC based Transaction Level Modeling (TLM) has matured as a standards-based approach to model SoC platforms for the purpose of Software development, system integration and verification. In response to the vast complexity of heterogeneous multi-processor platforms the "Architects View" is emerging as a new TLM use-case to address the architecture definition and application mapping by means of timing approximate transaction-level models. Integrated System-Level Modeling of Network-on-Chip Enabled Multi-Processor Platforms first gives a comprehensive update on recent developments in the area of SoC platforms and ESL design methodologies. The main contribution is the rigorous definition of a framework for modeling at the timing approximate level of abstraction. Subsequently this book presents a set of tools for the creation and exploration of timing approximate SoC platform models
UR  - http://dx.doi.org/10.1007/1-4020-4826-2
ER  -