TY  - BOOK
AU  - Chiang,Charles C.
AU  - Kawa,Jamil
ED  - SpringerLink (Online service)
TI  - Design for Manufacturability and Yield for Nano-Scale CMOS
T2  - Series on Integrated Circuits and Systems,
SN  - 9781402051883
U1  - 621.3815 23
PY  - 2007///
CY  - Dordrecht
PB  - Springer Netherlands
KW  - COMPUTER SCIENCE
KW  - SOFTWARE ENGINEERING
KW  - COMPUTER AIDED DESIGN
KW  - ELECTRONICS
KW  - SYSTEMS ENGINEERING
KW  - NANOTECHNOLOGY
KW  - CIRCUITS AND SYSTEMS
KW  - ELECTRONICS AND MICROELECTRONICS, INSTRUMENTATION
KW  - COMPUTER-AIDED ENGINEERING (CAD, CAE) AND DESIGN
KW  - PROCESSOR ARCHITECTURES
KW  - SOFTWARE ENGINEERING/PROGRAMMING AND OPERATING SYSTEMS
N1  - Random Defects -- Systematic Yield - Lithography -- Systematic Yield - Chemical Mechanical Polishing (CMP) -- Variability & Parametric Yield -- Design for Yield -- Yield Prediction -- Conclusions
N2  - As we approach the 32 nm CMOS technology node the design and manufacturing communities are dealing with a lithography system that has to print circuit artifacts that are significantly less than half the wavelength of the light source used, with new materials, with tighter pitches, and higher aspect ratio metallurgies. This reality has resulted in three main manufacturability issues that have to be addressed: printability, planarization, and intra-die variability. Addressing in depth the fundamentals impacting those three issues at all the stages of the design process is not a luxury one can ignore. Manufacturability and yield are now one and the same and are no longer a fabrication, packaging, and test concerns; they are the concern of the whole IC community. Yield and manufacturability have to be designed in, and they are everybody's responsibility. Design for Manufacturability and Yield for Nano-Scale CMOS walks the reader through all the aspects of manufacturability and yield in a nano-CMOS process and how to address each aspect at the proper design step starting with the design and layout of standard cells and how to yield-grade libraries for critical area and lithography artifacts through place and route, CMP model based simulation and dummy-fill insertion, mask planning, simulation and manufacturing, and through statistical design and statistical timing closure of the design. It alerts the designer to the pitfalls to watch for and to the good practices that can enhance a design's manufacturability and yield. This book is a must read book the serious practicing IC designer and an excellent primer for any graduate student intent on having a career in IC design or in EDA tool development
UR  - http://dx.doi.org/10.1007/978-1-4020-5188-3
ER  -