000			03222nam a22004095i 4500
001			978-0-387-23905-7
003			DE-He213
005			20250710083930.0
007			cr nn 008mamaa
008			100301s2005 xxu| s |||| 0|eng d
020			_a9780387239057 _a99780387239057
024	7		_a10.1007/b103124 _2doi
082	0	4	_a621.3 _223
100	1		_aQin, Zhanhai. _eauthor.
245	1	0	_aSymbolic Analysis and Reduction of VLSI Circuits _h[recurso electrónico] / _cby Zhanhai Qin, Sheldon X. D. Tan, Chung-Kuan Cheng.
264		1	_aBoston, MA : _bSpringer US, _c2005.
300			_aXXII, 283 p. _bonline resource.
336			_atext _btxt _2rdacontent
337			_acomputer _bc _2rdamedia
338			_arecurso en línea _bcr _2rdacarrier
347			_atext file _bPDF _2rda
505	0		_aFundamentals -- Basics Of Circuit Analysis -- Linear VLSI Circuits -- Model-Order Reduction -- Generalized Y-? Transformation - Fundamental Theory -- Generalized Y-? Transformation - Advance Topics -- Y-? Transformation: Application I - Model Stabilization -- Y-? Transformation: Application II - Realizable Parasitic Reduction -- Analog VLSI Circuits -- Topological Analysis of Passive Networks -- Exact Symbolic Analysis Using Determinant Decision Diagrams -- S-Expanded Determinant Decision Diagrams for Symbolic Analysis -- DDD Based Approximation for Analog Behavioral Modeling -- Hierarchical Symbolic Analysis and Hierarchical Model Order Reduction.
520			_aThe IC industry, including digital and analog circuit design houses, electrical design automation software vendors, library and IP providers, and foundries all face grand challenges in designing nanometer VLSI systems. The design productivity gap between nanometer VLSI technologies and today's design capabilities mainly comes from the exponentially growing complexity of VLSI systems due to relentless pushing for integration. The physical effects on the performance and reliability of these systems are becoming more pronounced. Efficient modeling and reduction of both the passive and active circuits is essential for hierarchical and IP-based reuse design paradigms. Symbolic Analysis and Reducation of VLSI Circuits presents the symbolic approach to the modeling and reduction of both the passive parasitic linear networks and active analog circuits. It reviews classic symbolic analysis methods and presents state-of-art developments for interconnect reduction and the behavioral modeling of active analog circuits. The text includes the most updated discoveries such as Y-Delta transformation and DDD-graph symbolic representation which allow analysis and modeling of much larger circuitry than ever before.
650		0	_aENGINEERING.
650		0	_aCOMPUTER ENGINEERING.
650	1	4	_aENGINEERING.
650	2	4	_aELECTRICAL ENGINEERING.
700	1		_aTan, Sheldon X. D. _eauthor.
700	1		_aCheng, Chung-Kuan. _eauthor.
710	2		_aSpringerLink (Online service)
773	0		_tSpringer eBooks
776	0	8	_iPrinted edition: _z9780387239040
856	4	0	_uhttp://dx.doi.org/10.1007/b103124 _zVer el texto completo en las instalaciones del CICY
912			_aZDB-2-ENG
942			_2ddc _cER
999			_c56279 _d56279