000 04350nam a22004935i 4500
001 978-0-387-26122-5
003 DE-He213
005 20250710083935.0
007 cr nn 008mamaa
008 100301s2006 xxu| s |||| 0|eng d
020 _a9780387261225
_a99780387261225
024 7 _a10.1007/b136837
_2doi
082 0 4 _a621.3815
_223
100 1 _aU, Seng-Pan.
_eauthor.
245 1 0 _aDesign of Very High-Frequency Multirate Switched-Capacitor Circuits
_h[recurso electrónico] :
_bExtending the Boundaries of CMOS Analog Front-End Filtering /
_cby Seng-Pan U, Rui Paulo Martins, José Epifânio Franca.
264 1 _aBoston, MA :
_bSpringer US,
_c2006.
300 _aXXXII, 227 p.
_bonline resource.
336 _atext
_btxt
_2rdacontent
337 _acomputer
_bc
_2rdamedia
338 _arecurso en línea
_bcr
_2rdacarrier
347 _atext file
_bPDF
_2rda
490 1 _aThe International Series in Engineering and Computer Science, Analog Circuits and Signal Processing,
_x0893-3405 ;
_v867
505 0 _aImproved Multirate Polyphase-Based Interpolation Structures -- Practical Multirate SC Circuit Design Considerations -- Gain- and Offset- Compensation for Multirate SC Circuits -- Design of a 108 MHz Multistage SC Video Interpolating Filter -- Design of a 320 MHz Frequency-Translated SC Bandpass Interpolating Filter -- Experimental Results -- Conclusions.
520 _aDesign of Very High-Frequency Multirate Switched-Capacitor Circuits presents the theory and the corresponding CMOS implementation of the novel multirate sampled-data analog interpolation technique which has its great potential on very high-frequency analog frond-end filtering due to its inherent dual advantage of reducing the speed of data-converters and DSP core together with the specification relaxation of the post continuous-time filtering. This technique completely eliminates the traditional phenomenon of sampled-and-hold frequency-shaping at the lower input sampling rate. Also, in order to tackle physical IC imperfections at very high frequency, the state-of-the-art circuit design and layout techniques for high-speed Switched-Capacitor (SC) circuits are comprehensively discussed: -Optimum circuit architecture tradeoff analysis -Simple speed and power trade-off analysis of active elements -High-order filtering response accuracy with respect to capacitor-ratio mismatches -Time-interleaved effect with respect to gain and offset mismatch -Time-interleaved effect with respect to timing-skew and random jitter with non-uniformly holding -Stage noise analysis and allocation scheme -Substrate and supply noise reduction -Gain-and offset-compensation techniques -High-bandwidth low-power amplifier design and layout -Very low timing-skew multiphase generation Two tailor-made optimum design examples in CMOS are presented. The first one achieves a 3-stage 8-fold SC interpolating filter with 5.5MHz bandwidth and 108MHz output sampling rate for a NTSC/PAL CCIR 601 digital video at 3 V. Another is a 15-tap 57MHz SC FIR bandpass interpolating filter with 4-fold sampling rate increase to 320MHz and the first-time embedded frequency band up-translation for DDFS system at 2.5V. The corresponding chip prototype achieves so far the highest operating frequency, highest filter order and highest center frequency with highest dynamic range under the lowest supply voltage when compared to the previously reported high-frequency SC filters in CMOS.
650 0 _aENGINEERING.
650 0 _aENGINEERING DESIGN.
650 0 _aELECTRONICS.
650 0 _aSYSTEMS ENGINEERING.
650 1 4 _aENGINEERING.
650 2 4 _aCIRCUITS AND SYSTEMS.
650 2 4 _aELECTRONIC AND COMPUTER ENGINEERING.
650 2 4 _aENGINEERING DESIGN.
650 2 4 _aELECTRONICS AND MICROELECTRONICS, INSTRUMENTATION.
700 1 _aMartins, Rui Paulo.
_eauthor.
700 1 _aFranca, José Epifânio.
_eauthor.
710 2 _aSpringerLink (Online service)
773 0 _tSpringer eBooks
776 0 8 _iPrinted edition:
_z9780387261218
830 0 _aThe International Series in Engineering and Computer Science, Analog Circuits and Signal Processing,
_x0893-3405 ;
_v867
856 4 0 _uhttp://dx.doi.org/10.1007/b136837
_zVer el texto completo en las instalaciones del CICY
912 _aZDB-2-ENG
942 _2ddc
_cER
999 _c56531
_d56531