000			03897nam a22004335i 4500
001			978-0-387-26173-7
003			DE-He213
005			20250710083935.0
007			cr nn 008mamaa
008			100301s2005 xxu| s |||| 0|eng d
020			_a9780387261737 _a99780387261737
024	7		_a10.1007/b137011 _2doi
082	0	4	_a621.3815 _223
100	1		_aVijayaraghavan, Srikanth. _eauthor.
245	1	2	_aA Practical Guide for SystemVerilog Assertions _h[recurso electrónico] / _cby Srikanth Vijayaraghavan, Meyyappan Ramanathan.
264		1	_aBoston, MA : _bSpringer US, _c2005.
300			_aXXVI, 334 p. With CD-ROM _bonline resource.
336			_atext _btxt _2rdacontent
337			_acomputer _bc _2rdamedia
338			_arecurso en línea _bcr _2rdacarrier
347			_atext file _bPDF _2rda
505	0		_aAssertion Based Verification -- to SVA -- SVA Simulation Methodology -- SVA for Finite State Machines -- SVA for Data Intensive Designs -- SVA for Memories -- SVA for Protocol Interface -- Checking the Checker.
520			_aSystemVerilog language consists of three very specific areas of constructs -- design, assertions and testbench. Assertions add a whole new dimension to the ASIC verification process. Assertions provide a better way to do verification proactively. Traditionally, engineers are used to writing verilog test benches that help simulate their design. Verilog is a procedural language and is very limited in capabilities to handle the complex Asic's built today. SystemVerilog assertions (SVA) are a declarative and temporal language that provides excellent control over time and parallelism. This provides the designers a very strong tool to solve their verification problems. While the language is built solid, the thinking is very different from the user's perspective when compared to standard verilog language. The concept is still very new and there is not enough expertise in the field to adopt this methodology and be successful. While the language has been defined very well, there is no practical guide that shows how to use the language to solve real verification problems. This book will be the practical guide that will help people to understand this new methodology. "Today's SoC complexity coupled with time-to-market and first-silicon success pressures make assertion based verification a requirement and this book points the way to effective use of assertions." Satish S. Iyengar, Director, ASIC Engineering, Crimson Microsystems, Inc. "This book benefits both the beginner and the more advanced users of SystemVerilog Assertions (SVA). First by introducing the concept of Assertion Based Verification (ABV) in a simple to understand way, then by discussing the myriad of ideas in a broader scope that SVA can accommodate. The many real life examples, provided throughout the book, are especially useful." Irwan Sie, Director, IC Design, ESS Technology, Inc. "SystemVerilog Assertions is a new language that can find and isolate bugs early in the design cycle. This book shows how to verify complex protocols and memories using SVA with seeral examples. This book is a good reference guide for both design and verification engineers." Derick Lin, Senior Director, Engineering, Airgo Networks, Inc.
650		0	_aENGINEERING.
650		0	_aELECTRONICS.
650		0	_aSYSTEMS ENGINEERING.
650	1	4	_aENGINEERING.
650	2	4	_aCIRCUITS AND SYSTEMS.
650	2	4	_aELECTRONIC AND COMPUTER ENGINEERING.
650	2	4	_aELECTRONICS AND MICROELECTRONICS, INSTRUMENTATION.
700	1		_aRamanathan, Meyyappan. _eauthor.
710	2		_aSpringerLink (Online service)
773	0		_tSpringer eBooks
776	0	8	_iPrinted edition: _z9780387260495
856	4	0	_uhttp://dx.doi.org/10.1007/b137011 _zVer el texto completo en las instalaciones del CICY
912			_aZDB-2-ENG
942			_2ddc _cER
999			_c56539 _d56539