000			03506nam a22005055i 4500
001			978-0-387-26399-1
003			DE-He213
005			20250710083936.0
007			cr nn 008mamaa
008			100301s2005 xxu| s |||| 0|eng d
020			_a9780387263991 _a99780387263991
024	7		_a10.1007/b137514 _2doi
082	0	4	_a621.3815 _223
100	1		_aMishra, Prabhat. _eauthor.
245	1	0	_aFunctional Verification of Programmable Embedded Architectures _h[recurso electrónico] : _bA Top-Down Approach / _cby Prabhat Mishra, Nikil D. Dutt.
264		1	_aBoston, MA : _bSpringer US, _c2005.
300			_aXIX, 180 p. _bonline resource.
336			_atext _btxt _2rdacontent
337			_acomputer _bc _2rdamedia
338			_arecurso en línea _bcr _2rdacarrier
347			_atext file _bPDF _2rda
505	0		_ato Functional Verification -- Architecture Specification -- Architecture Specification -- Validation of Specification -- Top-Down Validation -- Executable Model Generation -- Design Validation -- Functional Test Generation -- Future Directions -- Conclusions.
520			_aValidation of programmable architectures, consisting of processor cores, coprocessors, and memory subsystems, is one of the major bottlenecks in current System-on-Chip design methodology. A critical challenge in validation of such systems is the lack of a golden reference model. As a result, many existing validation techniques employ a bottom-up approach to design verification, where the functionality of an existing architecture is, in essence, reverse-engineered from its implementation. Traditional validation techniques employ different reference models depending on the abstraction level and verification task, resulting in potential inconsistencies between multiple reference models. This book presents a top-down validation methodology that complements the existing bottom-up approaches. It leverages the system architect's knowledge about the behavior of the design through architecture specification using an Architecture Description Language (ADL). The authors also address two fundamental challenges in functional verification: lack of a golden reference model, and lack of a comprehensive functional coverage metric. Functional Verification of Programmable Embedded Architectures: A Top-Down Approach is designed for students, researchers, CAD tool developers, designers, and managers interested in the development of tools, techniques and methodologies for system-level design, microprocessor validation, design space exploration and functional verification of embedded systems.
650		0	_aENGINEERING.
650		0	_aCOMPUTER SCIENCE.
650		0	_aSOFTWARE ENGINEERING.
650		0	_aCOMPUTER SYSTEM PERFORMANCE.
650		0	_aCOMPUTER AIDED DESIGN.
650		0	_aSYSTEMS ENGINEERING.
650	1	4	_aENGINEERING.
650	2	4	_aCIRCUITS AND SYSTEMS.
650	2	4	_aPROCESSOR ARCHITECTURES.
650	2	4	_aSPECIAL PURPOSE AND APPLICATION-BASED SYSTEMS.
650	2	4	_aCOMPUTER-AIDED ENGINEERING (CAD, CAE) AND DESIGN.
650	2	4	_aSYSTEM PERFORMANCE AND EVALUATION.
650	2	4	_aELECTRONIC AND COMPUTER ENGINEERING.
700	1		_aDutt, Nikil D. _eauthor.
710	2		_aSpringerLink (Online service)
773	0		_tSpringer eBooks
776	0	8	_iPrinted edition: _z9780387261430
856	4	0	_uhttp://dx.doi.org/10.1007/b137514 _zVer el texto completo en las instalaciones del CICY
912			_aZDB-2-ENG
942			_2ddc _cER
999			_c56574 _d56574