000			03904nam a22005175i 4500
001			978-0-387-31069-5
003			DE-He213
005			20250710083947.0
007			cr nn 008mamaa
008			100301s2006 xxu| s |||| 0|eng d
020			_a9780387310695 _a99780387310695
024	7		_a10.1007/978-0-387-31069-5 _2doi
082	0	4	_a621.3 _223
100	1		_aKastensmidt, Fernanda Lima. _eauthor.
245	1	0	_aFault-Tolerance Techniques for SRAM-based FPGAs _h[recurso electrónico] / _cby Fernanda Lima Kastensmidt, Luigi Carro, Ricardo Reis.
264		1	_aBoston, MA : _bSpringer US, _c2006.
300			_aXV, 183 p. _bonline resource.
336			_atext _btxt _2rdacontent
337			_acomputer _bc _2rdamedia
338			_arecurso en línea _bcr _2rdacarrier
347			_atext file _bPDF _2rda
505	0		_aRadiation Effects in Integrated Circuits -- Single Event Upset (SEU) Mitigation Techniques -- Architectural SEU Mitigation Techniques -- High-Level SEU Mitigation Techniques -- Triple Modular Redundancy (TMR) Robustness -- Designing and Testing a TMR Micro-Controller -- Reducing TMR Overheads: Part I -- Reducing TMR Overheads: Part II -- Final Remarks.
520			_aFault-tolerance in integrated circuits is not an exclusive concern regarding space designers or highly-reliable application engineers. Rather, designers of next generation products must cope with reduced margin noises due to technological advances. The continuous evolution of the fabrication technology process of semiconductor components, in terms of transistor geometry shrinking, power supply, speed, and logic density, has significantly reduced the reliability of very deep submicron integrated circuits, in face of the various internal and external sources of noise. The very popular Field Programmable Gate Arrays, customizable by SRAM cells, are a consequence of the integrated circuit evolution with millions of memory cells to implement the logic, embedded memories, routing, and more recently with embedded microprocessors cores. These re-programmable systems-on-chip platforms must be fault-tolerant to cope with present days requirements. This book discusses fault-tolerance techniques for SRAM-based Field Programmable Gate Arrays (FPGAs). It starts by showing the model of the problem and the upset effects in the programmable architecture. In the sequence, it shows the main fault tolerance techniques used nowadays to protect integrated circuits against errors. A large set of methods for designing fault tolerance systems in SRAM-based FPGAs is described. Some presented techniques are based on developing a new fault-tolerant architecture with new robustness FPGA elements. Other techniques are based on protecting the high-level hardware description before the synthesis in the FPGA. The reader has the flexibility of choosing the most suitable fault-tolerance technique for its project and to compare a set of fault tolerant techniques for programmable logic applications.
650		0	_aENGINEERING.
650		0	_aLOGIC DESIGN.
650		0	_aOPERATING SYSTEMS (COMPUTERS).
650		0	_aENGINEERING DESIGN.
650		0	_aELECTRONICS.
650		0	_aOPTICAL MATERIALS.
650	1	4	_aENGINEERING.
650	2	4	_aELECTRONIC AND COMPUTER ENGINEERING.
650	2	4	_aOPTICAL AND ELECTRONIC MATERIALS.
650	2	4	_aELECTRONICS AND MICROELECTRONICS, INSTRUMENTATION.
650	2	4	_aENGINEERING DESIGN.
650	2	4	_aPERFORMANCE AND RELIABILITY.
650	2	4	_aLOGIC DESIGN.
700	1		_aCarro, Luigi. _eauthor.
700	1		_aReis, Ricardo. _eauthor.
710	2		_aSpringerLink (Online service)
773	0		_tSpringer eBooks
776	0	8	_iPrinted edition: _z9780387310688
856	4	0	_uhttp://dx.doi.org/10.1007/978-0-387-31069-5 _zVer el texto completo en las instalaciones del CICY
912			_aZDB-2-ENG
942			_2ddc _cER
999			_c57100 _d57100