000			03087nam a22004575i 4500
001			978-0-387-31275-0
003			DE-He213
005			20250710083948.0
007			cr nn 008mamaa
008			100301s2006 xxu| s |||| 0|eng d
020			_a9780387312750 _a99780387312750
024	7		_a10.1007/0-387-31275-7 _2doi
082	0	4	_a621.3815 _223
100	1		_aBergeron, Janick. _eauthor.
245	1	0	_aWriting Testbenches using System Verilog _h[recurso electrónico] / _cby Janick Bergeron.
264		1	_aBoston, MA : _bSpringer US : _bImprint: Springer, _c2006.
300			_aXXVI, 412 p. _bonline resource.
336			_atext _btxt _2rdacontent
337			_acomputer _bc _2rdamedia
338			_arecurso en línea _bcr _2rdacarrier
347			_atext file _bPDF _2rda
505	0		_aWhat is Verification? -- Verification Technologies -- The Verification Plan -- High-Level Modeling -- Stimulus and Response -- Architecting Testbenches -- Simulation Management.
520			_aVerification is too often approached in an ad hoc fashion. Visually inspecting simulation results is no longer feasible and the directed test-case methodology is reaching its limit. Moore's Law demands a productivity revolution in functional verification methodology. Writing Testbenches Using SystemVerilog offers a clear blueprint of a verification process that aims for first-time success using the SystemVerilog language. From simulators to source management tools, from specification to functional coverage, from I's and O's to high-level abstractions, from interfaces to bus-functional models, from transactions to self-checking testbenches, from directed testcases to constrained random generators, from behavioral models to regression suites, this book covers it all. Writing Testbenches Using SystemVerilog presents many of the functional verification features that were added to the Verilog language as part of SystemVerilog. Interfaces, virtual modports, classes, program blocks, clocking blocks and others SystemVerilog features are introduced within a coherent verification methodology and usage model. Writing Testbenches Using SystemVerilog introduces the reader to all elements of a modern, scalable verification methodology. It is an introduction and prelude to the verification methodology detailed in the Verification Methodology Manual for SystemVerilog.
650		0	_aENGINEERING.
650		0	_aCOMPUTER AIDED DESIGN.
650		0	_aSYSTEM SAFETY.
650		0	_aCOMPUTER ENGINEERING.
650		0	_aSYSTEMS ENGINEERING.
650	1	4	_aENGINEERING.
650	2	4	_aCIRCUITS AND SYSTEMS.
650	2	4	_aCOMPUTER-AIDED ENGINEERING (CAD, CAE) AND DESIGN.
650	2	4	_aELECTRICAL ENGINEERING.
650	2	4	_aQUALITY CONTROL, RELIABILITY, SAFETY AND RISK.
710	2		_aSpringerLink (Online service)
773	0		_tSpringer eBooks
776	0	8	_iPrinted edition: _z9780387292212
856	4	0	_uhttp://dx.doi.org/10.1007/0-387-31275-7 _zVer el texto completo en las instalaciones del CICY
912			_aZDB-2-ENG
942			_2ddc _cER
999			_c57131 _d57131