000			05116nam a22004695i 4500
001			978-0-387-32500-2
003			DE-He213
005			20250710083949.0
007			cr nn 008mamaa
008			100301s2007 xxu| s |||| 0|eng d
020			_a9780387325002 _a99780387325002
024	7		_a10.1007/0-387-32500-X _2doi
082	0	4	_a621.3815 _223
100	1		_aReis, Ricardo. _eeditor.
245	1	0	_aDesign of Systems on a Chip: Design and Test _h[recurso electrónico] / _cedited by Ricardo Reis, Marcelo Lubaszewski, Jochen A.G. Jess.
264		1	_aBoston, MA : _bSpringer US, _c2007.
300			_aX, 232 p. _bonline resource.
336			_atext _btxt _2rdacontent
337			_acomputer _bc _2rdamedia
338			_arecurso en línea _bcr _2rdacarrier
347			_atext file _bPDF _2rda
505	0		_aDesign of Systems on a Chip -- Microsystems Technology and Applications -- Core Architectures for Digital Media and the Associated Compilation Techniques -- Past, Present and Future of Microprocessors -- Physical Design Automation -- Behavioral Synthesis: an Overview -- Hardware/Software co-design -- Test and Design-for-Test: from Circuits to Integrated Systems -- Synthesis of FPGAs and Testable ASICs -- Testable Design and Testing of Microsystems -- Embedded Core-based System-on-Chip Test Strategies.
520			_aDesign of Systems on a Chip: Design&Test is the second of two volumes addressing the design challenges associated with new generations of the semiconductor technology. The various chapters are the compilations of tutorials presented at workshops in the recent years by prominent authors from all over the world. Technology, productivity and quality are the main aspects under consideration to establish the major requirements for the design and test of upcoming systems on a chip. In particular this second book include contributions on three different, but complementary axes: core design, computer-aided design tools and test methods. A collection of chapters deal with the heterogeneity aspect of core designs, showing the diversity of parts that may share the same substrate in a state-of-the-art system on a chip. The second part of the book discusses CAD in three different levels of design abstraction, from system level to physical design. The third part deals with test methods. The topic is addressed from different viewpoints: in terms of chip complexity, test is discussed from the core and system prospective; in terms of signal heterogeneity, the digital, mixed-signal and microsystem prospective are considered. Fault-tolerance in integrated circuits is not an exclusive concern regarding space designers or highly-reliable application engineers. Rather, designers of next generation products must cope with reduced margin noises due to technological advances. The continuous evolution of the fabrication technology process of semiconductor components, in terms of transistor geometry shrinking, power supply, speed, and logic density, has significantly reduced the reliability of very deep submicron integrated circuits, in face of the various internal and external sources of noise. The very popular Field Programmable Gate Arrays, customizable by SRAM cells, are a consequence of the integrated circuit evolution with millions of memory cells to implement the logic, embedded memories, routing, and more recently with embedded microprocessors cores. These re-programmable systems-on-chip platforms must be fault-tolerant to cope with present days requirements. This book discusses fault-tolerance techniques for SRAM-based Field Programmable Gate Arrays (FPGAs). It starts by showing the model of the problem and the upset effects in the programmable architecture. In the sequence, it shows the main fault tolerance techniques used nowadays to protect integrated circuits against errors. A large set of methods for designing fault tolerance systems in SRAM-based FPGAs is described. Some presented techniques are based on developing a new fault-tolerant architecture with new robustness FPGA elements. Other techniques are based on protecting the high-level hardware description before the synthesis in the FPGA. The reader has the flexibility of choosing the most suitable fault-tolerance technique for its project and to compare a set of fault tolerant techniques for programmable logic applications.
650		0	_aENGINEERING.
650		0	_aENGINEERING DESIGN.
650		0	_aELECTRONICS.
650		0	_aSYSTEMS ENGINEERING.
650	1	4	_aENGINEERING.
650	2	4	_aCIRCUITS AND SYSTEMS.
650	2	4	_aELECTRONIC AND COMPUTER ENGINEERING.
650	2	4	_aENGINEERING DESIGN.
650	2	4	_aELECTRONICS AND MICROELECTRONICS, INSTRUMENTATION.
700	1		_aLubaszewski, Marcelo. _eeditor.
700	1		_aJess, Jochen A.G. _eeditor.
710	2		_aSpringerLink (Online service)
773	0		_tSpringer eBooks
776	0	8	_iPrinted edition: _z9780387324999
856	4	0	_uhttp://dx.doi.org/10.1007/0-387-32500-X _zVer el texto completo en las instalaciones del CICY
912			_aZDB-2-ENG
942			_2ddc _cER
999			_c57183 _d57183