000			03390nam a22004815i 4500
001			978-0-387-46547-0
003			DE-He213
005			20250710084001.0
007			cr nn 008mamaa
008			100301s2007 xxu| s |||| 0|eng d
020			_a9780387465470 _a99780387465470
024	7		_a10.1007/0-387-46547-2 _2doi
082	0	4	_a621.3815 _223
100	1		_aSachdev, Manoj. _eeditor.
245	1	0	_aDefect-Oriented Testing for Nano-Metric CMOS VLSI Circuits _h[recurso electrónico] : _b2nd Edition / _cedited by Manoj Sachdev, José Pineda de Gyvez.
264		1	_aBoston, MA : _bSpringer US, _c2007.
300			_aXXI, 328 p. _bonline resource.
336			_atext _btxt _2rdacontent
337			_acomputer _bc _2rdamedia
338			_arecurso en línea _bcr _2rdacarrier
347			_atext file _bPDF _2rda
490	1		_aFrontiers in Electronic Testing, _x0929-1296 ; _v34
505	0		_aFunctional and Parametric Defect Models -- Digital CMOS Fault Modeling -- Defects in Logic Circuits and their Test Implications -- Testing Defects and Parametric Variations in RAMs -- Defect-Oriented Analog Testing -- Yield Engineering -- Conclusion.
520			_aFailures of nano-metric technologies owing to defects and shrinking process tolerances give rise to significant challenges for IC testing. As the variation of fundamental parameters such as channel length, threshold voltage, thin oxide thickness and interconnect dimensions goes well beyond acceptable limits, new test methodologies and a deeper insight into the physics of defect-fault mappings are needed. In Defect-Oriented Testing for Nano-Metric CMOS VLSI Circuits state of the art of defect-oriented testing is presented from both a theoretical approach as well as from a practical point of view. Step-by-step handling of defect modeling, defect-oriented testing, yield modeling and its usage in common economics practices enables deeper understanding of concepts. The progression developed in this book is essential to understand new test methodologies, algorithms and industrial practices. Without the insight into the physics of nano-metric technologies, it would be hard to develop system-level test strategies that yield a high IC fault coverage. Obviously, the work on defect-oriented testing presented in the book is not final, and it is an evolving field with interesting challenges imposed by the ever-changing nature of nano-metric technologies. Test and design practitioners from academia and industry will find that Defect-Oriented Testing for Nano-Metric CMOS VLSI Circuits lays the foundations for further pioneering work.
650		0	_aENGINEERING.
650		0	_aENGINEERING DESIGN.
650		0	_aELECTRONICS.
650		0	_aSYSTEMS ENGINEERING.
650	1	4	_aENGINEERING.
650	2	4	_aCIRCUITS AND SYSTEMS.
650	2	4	_aELECTRONIC AND COMPUTER ENGINEERING.
650	2	4	_aENGINEERING DESIGN.
650	2	4	_aELECTRONICS AND MICROELECTRONICS, INSTRUMENTATION.
700	1		_aGyvez, José Pineda de. _eeditor.
710	2		_aSpringerLink (Online service)
773	0		_tSpringer eBooks
776	0	8	_iPrinted edition: _z9780387465463
830		0	_aFrontiers in Electronic Testing, _x0929-1296 ; _v34
856	4	0	_uhttp://dx.doi.org/10.1007/0-387-46547-2 _zVer el texto completo en las instalaciones del CICY
912			_aZDB-2-ENG
942			_2ddc _cER
999			_c57712 _d57712