000			04362nam a22004935i 4500
001			978-0-387-71819-4
003			DE-He213
005			20250710084013.0
007			cr nn 008mamaa
008			100301s2007 xxu| s |||| 0|eng d
020			_a9780387718194 _a99780387718194
024	7		_a10.1007/978-0-387-71819-4 _2doi
082	0	4	_a621.3815 _223
100	1		_aKeating, Michael. _eauthor.
245	1	0	_aLow Power Methodology Manual _h[recurso electrónico] : _bFor System-on-Chip Design / _cby Michael Keating, David Flynn, Robert Aitken, Alan Gibbons, Kaijian Shi.
264		1	_aBoston, MA : _bSpringer US, _c2007.
300			_aXVI, 304 p. _bonline resource.
336			_atext _btxt _2rdacontent
337			_acomputer _bc _2rdamedia
338			_arecurso en línea _bcr _2rdacarrier
347			_atext file _bPDF _2rda
505	0		_aStandard Low Power Methods -- Multi-Voltage Design -- Power Gating Overview -- Designing Power Gating -- Architectural Issues for Power Gating -- A Power Gating Example -- IP Design for Low Power -- Frequency and Voltage Scaling Design -- Examples of Voltage and Frequency Scaling Design -- Implementing Multi-Voltage, Power Gated Designs -- Physical Libraries -- Retention Register Design -- Design of the Power Switching Network.
520			_a"Tools alone aren't enough to reduce dynamic and leakage power in complex chip designs - a well-planned methodology is needed. Following in the footsteps of the successful Reuse Methodology Manual (RMM), authors from ARM and Synopsys have written this Low Power Methodology Manual (LPMM) to describe [such] [a] low-power methodology with a practical, step-by-step approach." Richard Goering, Software Editor, EE Times "Excellent compendium of low-power techniques and guidelines with balanced content spanning theory and practical implementation. The LPMM is a very welcome addition to the field of low power SoC implementation that has for many years operated in a largely ad-hoc fashion." Sujeeth Joseph, Chief Architect - Semiconductor & Systems Solutions Unit, Wipro Technologies "The LPMM enables broader adoption of aggressive power management techniques based on extensive experience and silicon example with real data that every SOC designer can use to meet the difficulties faced in managing the power issues in deep submicron designs" Anil Mankar, Sr VP Worldwide Core Engineering and Chief Development Officer, Conexant Systems Inc. "Managing power, at 90nm and below, introduces significant challenges to design flow. The LPMM is a timely and immediately useful book that shows how combination of tools, IP and methodology can be used together to address power management." Nick Salter, Head of Chip Integration, CSR plc. ABOUT THE AUTHORS: Michael Keating is a Synopsys Fellow in the company's Advanced Technology Group, focusing on IP development methodology, hardware and software design quality and low power design. David Flynn is an ARM R&D Fellow and has been with the company since 1991, specializing in low power System-on-Chip IP deployment and methodology. Robert Aitken is an ARM R&D Fellow. His areas of responsibility include memory architecture, design for testability and design for manufacturability. Alan Gibbons is a Principal Engineer at Synopsys, with a focus on development of advanced methodology and technology for ARM processor-based system design. Kaijian Shi is a Principal Consultant in the Professional Services Group of Synopsys, specializing in low power design methodology and implementation.
650		0	_aENGINEERING.
650		0	_aCOMPUTER HARDWARE.
650		0	_aELECTRONICS.
650		0	_aSYSTEMS ENGINEERING.
650	1	4	_aENGINEERING.
650	2	4	_aCIRCUITS AND SYSTEMS.
650	2	4	_aELECTRONICS AND MICROELECTRONICS, INSTRUMENTATION.
650	2	4	_aELECTRONIC AND COMPUTER ENGINEERING.
650	2	4	_aCOMPUTER HARDWARE.
700	1		_aFlynn, David. _eauthor.
700	1		_aAitken, Robert. _eauthor.
700	1		_aGibbons, Alan. _eauthor.
700	1		_aShi, Kaijian. _eauthor.
710	2		_aSpringerLink (Online service)
773	0		_tSpringer eBooks
776	0	8	_iPrinted edition: _z9780387718187
856	4	0	_uhttp://dx.doi.org/10.1007/978-0-387-71819-4 _zVer el texto completo en las instalaciones del CICY
912			_aZDB-2-ENG
942			_2ddc _cER
999			_c58300 _d58300