000			03864nam a22005055i 4500
001			978-0-387-76474-0
003			DE-He213
005			20250710084024.0
007			cr nn 008mamaa
008			100301s2008 xxu| s |||| 0|eng d
020			_a9780387764740 _a99780387764740
024	7		_a10.1007/978-0-387-76474-0 _2doi
100	1		_aPatra, Priyardarsan. _eauthor.
245	1	0	_aLow-Power High-Level Synthesis for Nanoscale CMOS Circuits _h[recurso electrónico] / _cby Priyardarsan Patra, Elias Kougianos, Nagarajan Ranganathan, Saraju P. Mohanty.
264		1	_aBoston, MA : _bSpringer US, _c2008.
300			_bonline resource.
336			_atext _btxt _2rdacontent
337			_acomputer _bc _2rdamedia
338			_arecurso en línea _bcr _2rdacarrier
347			_atext file _bPDF _2rda
505	0		_aHigh-Level Synthesis Fundamentals -- Power Modeling and Estimation at Transistor and Logic Gate Levels -- Architectural Power Modeling and Estimation -- Power Reduction Fundamentals -- Energy or Average Power Reduction -- Peak Power Reduction -- Transient Power Reduction -- Leakage Power Reduction -- Conclusions and Future Direction.
520			_aLow-Power High-Level Synthesis for Nanoscale CMOS Circuits addresses the need for analysis, characterization, estimation, and optimization of the various forms of power dissipation in the presence of process variations of nano-CMOS technologies. The authors show very large-scale integration (VLSI) researchers and engineers how to minimize the different types of power consumption of digital circuits. The material deals primarily with high-level (architectural or behavioral) energy dissipation because the behavioral level is not as highly abstracted as the system level nor is it as complex as the gate/transistor level. At the behavioral level there is a balanced degree of freedom to explore power reduction mechanisms, the power reduction opportunities are greater, and it can cost-effectively help in investigating lower power design alternatives prior to actual circuit layout or silicon implementation. The book is a self-contained low-power, high-level synthesis text for Nanoscale VLSI design engineers and researchers. Each chapter has simple relevant examples for a better grasp of the principles presented. Several algorithms are given to provide a better understanding of the underlying concepts. The initial chapters deal with the basics of high-level synthesis, power dissipation mechanisms, and power estimation. In subsequent parts of the text, a detailed discussion of methodologies for the reduction of different types of power is presented including: • Power Reduction Fundamentals • Energy or Average Power Reduction • Peak Power Reduction • Transient Power Reduction • Leakage Power Reduction Low-Power High-Level Synthesis for Nanoscale CMOS Circuits provides a valuable resource for the design of low-power CMOS circuits.
650		0	_aENGINEERING.
650		0	_aCOMPUTER HARDWARE.
650		0	_aCOMPUTER AIDED DESIGN.
650		0	_aCOMPUTER ENGINEERING.
650		0	_aELECTRONICS.
650		0	_aSYSTEMS ENGINEERING.
650	1	4	_aENGINEERING.
650	2	4	_aELECTRICAL ENGINEERING.
650	2	4	_aCOMPUTER HARDWARE.
650	2	4	_aCOMPUTER-AIDED ENGINEERING (CAD, CAE) AND DESIGN.
650	2	4	_aELECTRONICS AND MICROELECTRONICS, INSTRUMENTATION.
650	2	4	_aCIRCUITS AND SYSTEMS.
700	1		_aKougianos, Elias. _eauthor.
700	1		_aRanganathan, Nagarajan. _eauthor.
700	1		_aMohanty, Saraju P. _eauthor.
710	2		_aSpringerLink (Online service)
773	0		_tSpringer eBooks
776	0	8	_iPrinted edition: _z9780387764733
856	4	0	_uhttp://dx.doi.org/10.1007/978-0-387-76474-0 _zVer el texto completo en las instalaciones del CICY
912			_aZDB-2-ENG
942			_2ddc _cER
999			_c58768 _d58768