000			03333nam a22004815i 4500
001			978-0-387-76534-1
003			DE-He213
005			20250710084024.0
007			cr nn 008mamaa
008			100301s2008 xxu| s |||| 0|eng d
020			_a9780387765341 _a99780387765341
024	7		_a10.1007/978-0-387-76534-1 _2doi
100	1		_aTan, Chuan Seng. _eeditor.
245	1	0	_aWafer Level 3-D ICs Process Technology _h[recurso electrónico] / _cedited by Chuan Seng Tan, Ronald J. Gutmann, L. Rafael Reif.
264		1	_aBoston, MA : _bSpringer US, _c2008.
300			_aXII, 410p. _bonline resource.
336			_atext _btxt _2rdacontent
337			_acomputer _bc _2rdamedia
338			_arecurso en línea _bcr _2rdacarrier
347			_atext file _bPDF _2rda
490	1		_aIntegrated Circuits and Systems, _x1558-9412
505	0		_aOverview of Wafer-Level 3D ICs -- Monolithic 3D Integrated Circuits -- Stacked CMOS Technologies -- Wafer-Bonding Technologies and Strategies for 3D ICs -- Through-Silicon Via Fabrication, Backgrind, and Handle Wafer Technologies -- Cu Wafer Bonding for 3D IC Applications -- Cu/Sn Solid-Liquid Interdiffusion Bonding -- An SOI-Based 3D Circuit Integration Technology -- 3D Fabrication Options for High-Performance CMOS Technology -- 3D Integration Based upon Dielectric Adhesive Bonding -- Direct Hybrid Bonding -- 3D Memory -- Circuit Architectures for 3D Integration -- Thermal Challenges of 3D ICs -- Status and Outlook.
520			_aWafer Level 3-D ICs Process Technology focuses on foundry-based process technology that enables the fabrication of 3-D ICs. The core of the book discusses alternative technology platforms for pre-packaging wafer level 3-D ICs, with an emphasis on wafer-to-wafer stacking. Driven by the need for improved performance, a number of companies, consortia and universities are researching methods to use short, monolithically-fabricated, vertical interconnections to replace the long interconnects found in 2-D ICs. Stacking disparate technologies to provide various combinations of densely-packed functions, such as logic, memory, MEMS, displays, RF, mixed-signal, sensors, and power delivery is potentially possible with 3-D heterogeneous integration, making this technology the "Holy Grail" of system integration. Wafer Level 3-D ICs Process Technology is an edited book based on chapters contributed by various experts in the fields of wafer-level 3-D ICs process technology and applications enabled by 3-D integration.
650		0	_aENGINEERING.
650		0	_aELECTRONICS.
650		0	_aOPTICAL MATERIALS.
650		0	_aSURFACES (PHYSICS).
650	1	4	_aENGINEERING.
650	2	4	_aELECTRONICS AND MICROELECTRONICS, INSTRUMENTATION.
650	2	4	_aOPTICAL AND ELECTRONIC MATERIALS.
650	2	4	_aSURFACES AND INTERFACES, THIN FILMS.
650	2	4	_aENGINEERING, GENERAL.
700	1		_aGutmann, Ronald J. _eeditor.
700	1		_aReif, L. Rafael. _eeditor.
710	2		_aSpringerLink (Online service)
773	0		_tSpringer eBooks
776	0	8	_iPrinted edition: _z9780387765327
830		0	_aIntegrated Circuits and Systems, _x1558-9412
856	4	0	_uhttp://dx.doi.org/10.1007/978-0-387-76534-1 _zVer el texto completo en las instalaciones del CICY
912			_aZDB-2-ENG
942			_2ddc _cER
999			_c58787 _d58787