000			03020nam a22004455i 4500
001			978-0-387-93820-2
003			DE-He213
005			20251006084432.0
007			cr nn 008mamaa
008			100301s2009 xxu| s |||| 0|eng d
020			_a9780387938202
020			_a99780387938202
024	7		_a10.1007/978-0-387-93820-2 _2doi
100	1		_aChadha, Rakesh. _eauthor.
245	1	0	_aStatic Timing Analysis for Nanometer Designs _h[electronic resource] : _bA Practical Approach / _cby Rakesh Chadha, J. Bhasker.
264		1	_aBoston, MA : _bSpringer US, _c2009.
300			_bonline resource.
336			_atext _btxt _2rdacontent
337			_acomputer _bc _2rdamedia
338			_aonline resource _bcr _2rdacarrier
347			_atext file _bPDF _2rda
505	0		_aSTA Concepts -- Standard Cell Library -- Interconnect Parasitics -- Delay Calculation -- Crosstalk and Noise -- Configuring the STA Environment -- Timing Verification -- Interface Analysis -- Robust Verification.
520			_aStatic Timing Analysis for Nanometer Designs: A Practical Approach is a reference for both beginners as well as professionals working in the area of static timing analysis for semiconductors. This book provides a blend of underlying theoretical background and in-depth coverage of timing verification using static timing analysis. The relevant topics such as cell and interconnect modeling, timing calculation, and crosstalk, which can impact the timing of a nanometer design are covered in detail. Timing checks at various process, environment, and interconnect corners, including on-chip variations, are explained in detail. Verification of hierarchal building blocks, full chip, including timing verification of special IO interfaces are covered in detail. Appendices provide complete coverage of SDC, SDF, and SPEF formats. This book is written for professionals working in the area of chip design, timing verification of ASICs and also for graduate students specializing in logic and chip design. Professionals who are beginning to use static timing analysis or are already well-versed in static timing analysis will find this book useful. Static Timing Analysis for Nanometer Designs serves as a reference for a graduate course in chip design and as a text for a course in timing verification for working engineers.
650		0	_aENGINEERING.
650		0	_aCOMPUTER AIDED DESIGN.
650		0	_aELECTRONICS.
650		0	_aSYSTEMS ENGINEERING.
650	1	4	_aENGINEERING.
650	2	4	_aCOMPUTER-AIDED ENGINEERING (CAD, CAE) AND DESIGN.
650	2	4	_aELECTRONICS AND MICROELECTRONICS, INSTRUMENTATION.
650	2	4	_aCIRCUITS AND SYSTEMS.
700	1		_aBhasker, J. _eauthor.
710	2		_aSpringerLink (Online service)
773	0		_tSpringer eBooks
776	0	8	_iPrinted edition: _z9780387938196
856	4	0	_uhttp://dx.doi.org/10.1007/978-0-387-93820-2 _zVer el texto completo en las instalaciones del CICY
912			_aZDB-2-ENG
942			_2ddc _cER
999			_c59539 _d59539