000			03553nam a22005295i 4500
001			978-1-4020-4826-5
003			DE-He213
005			20251006084515.0
007			cr nn 008mamaa
008			100301s2006 ne | s |||| 0|eng d
020			_a9781402048265
020			_a99781402048265
024	7		_a10.1007/1-4020-4826-2 _2doi
082	0	4	_a621.3815 _223
100	1		_aKogel, Tim. _eauthor.
245	1	0	_aIntegrated System-Level Modeling of Network-on-Chip enabled Multi-Processor Platforms _h[electronic resource] / _cby Tim Kogel, Rainer Leupers, Heinrich Meyr.
264		1	_aDordrecht : _bSpringer Netherlands, _c2006.
300			_aXIV, 199 p. _bonline resource.
336			_atext _btxt _2rdacontent
337			_acomputer _bc _2rdamedia
338			_aonline resource _bcr _2rdacarrier
347			_atext file _bPDF _2rda
505	0		_aForeword. Preface -- 1. Introduction -- 2. Embedded SOC Applications -- 3. Classification of Platform Elements -- 4. System Level Design Principles -- 5. Related Work -- 6. Methodology Overview -- 7. Unified Timing Model -- 8. MP-SOC Simulation Framework -- 9. Case Study -- 10. Summary -- Appendices. A: The OSCI TLM Standard. B: The OCPIP TL3 Channel. C: The Architects View Framework -- List of Figures. List of Tables. References -- Index.
520			_aThe drastic performance, flexibility and energy-efficiency requirements of embedded applications drive the System-on-Chip integration towards heterogeneous multiprocessor platforms. Electronic System Level (ESL) design methodologies and tools have emerged to tackle the challenges of such complex SoC designs prior to RTL and silicon availability. In particular SystemC based Transaction Level Modeling (TLM) has matured as a standards-based approach to model SoC platforms for the purpose of Software development, system integration and verification. In response to the vast complexity of heterogeneous multi-processor platforms the "Architects View" is emerging as a new TLM use-case to address the architecture definition and application mapping by means of timing approximate transaction-level models. Integrated System-Level Modeling of Network-on-Chip Enabled Multi-Processor Platforms first gives a comprehensive update on recent developments in the area of SoC platforms and ESL design methodologies. The main contribution is the rigorous definition of a framework for modeling at the timing approximate level of abstraction. Subsequently this book presents a set of tools for the creation and exploration of timing approximate SoC platform models.
650		0	_aENGINEERING.
650		0	_aSOFTWARE ENGINEERING.
650		0	_aCOMPUTER SIMULATION.
650		0	_aCOMPUTER AIDED DESIGN.
650		0	_aELECTRONICS.
650		0	_aSYSTEMS ENGINEERING.
650	1	4	_aENGINEERING.
650	2	4	_aCIRCUITS AND SYSTEMS.
650	2	4	_aELECTRONICS AND MICROELECTRONICS, INSTRUMENTATION.
650	2	4	_aSIMULATION AND MODELING.
650	2	4	_aSOFTWARE ENGINEERING/PROGRAMMING AND OPERATING SYSTEMS.
650	2	4	_aSPECIAL PURPOSE AND APPLICATION-BASED SYSTEMS.
650	2	4	_aCOMPUTER-AIDED ENGINEERING (CAD, CAE) AND DESIGN.
700	1		_aLeupers, Rainer. _eauthor.
700	1		_aMeyr, Heinrich. _eauthor.
710	2		_aSpringerLink (Online service)
773	0		_tSpringer eBooks
776	0	8	_iPrinted edition: _z9781402048258
856	4	0	_uhttp://dx.doi.org/10.1007/1-4020-4826-2 _zVer el texto completo en las instalaciones del CICY
912			_aZDB-2-ENG
942			_2ddc _cER
999			_c61023 _d61023