000			03347nam a22005175i 4500
001			978-1-4020-5081-7
003			DE-He213
005			20251006084518.0
007			cr nn 008mamaa
008			100301s2007 ne | s |||| 0|eng d
020			_a9781402050817
020			_a99781402050817
024	7		_a10.1007/1-4020-5081-X _2doi
082	0	4	_a621.3815 _223
100	1		_aHenzler, Stephan. _eauthor.
245	1	0	_aPower Management of Digital Circuits in Deep Sub-Micron CMOS Technologies _h[electronic resource] / _cby Stephan Henzler.
264		1	_aDordrecht : _bSpringer Netherlands, _c2007.
300			_aXVI, 183 p. 127 illus. _bonline resource.
336			_atext _btxt _2rdacontent
337			_acomputer _bc _2rdamedia
338			_aonline resource _bcr _2rdacarrier
347			_atext file _bPDF _2rda
490	1		_aAdvanced Microelectronics, _x1437-0387 ; _v25
505	0		_aTO LOW-POWER DIGITAL INTEGRATED CIRCUIT DESIGN -- LOGIC WITH MULTIPLE SUPPLY VOLTAGES -- LOGIC WITH MULTIPLE THRESHOLD VOLTAGES -- FORCING OF TRANSISTOR STACKS -- POWER GATING -- CONCLUSION.
520			_aIn the deep sub-micron regime, the power consumption has become one of the most important issues for competitive design of digital circuits. Due to dramatically increasing leakage currents, the power consumption does not take advantage of technology scaling as before. State-of-art power reduction techniques like the use of multiple supply and threshold voltages, transistor stack forcing and power gating are discussed with respect to implementation and power saving capability. Focus is given especially on technology dependencies, process variations and technology scaling. Design and implementation issues are discussed with respect to the trade-off between power reduction, performance degradation, and system level constraints. A complete top-down design flow is demonstrated for power gating techniques introducing new design methodologies for the switch sizing task and circuit blocks for data-retention and block activation. The leakage reduction ratio and the minimum power-down time are introduced as figures of merit to describe the power gating technique on system level and give a relation to physical circuit parameters. Power Management of Digital Circuits in Deep Sub-Micron CMOS Technologies mainly deals with circuit design but also addresses the interface between circuit and system level design on the one side and between circuit and physical design on the other side.
650		0	_aENGINEERING.
650		0	_aPARTICLES (NUCLEAR PHYSICS).
650		0	_aELECTRONICS.
650		0	_aSYSTEMS ENGINEERING.
650		0	_aNANOTECHNOLOGY.
650	1	4	_aENGINEERING.
650	2	4	_aCIRCUITS AND SYSTEMS.
650	2	4	_aPOWER ENGINEERING.
650	2	4	_aELECTRONIC AND COMPUTER ENGINEERING.
650	2	4	_aSOLID STATE PHYSICS AND SPECTROSCOPY.
650	2	4	_aELECTRONICS AND MICROELECTRONICS, INSTRUMENTATION.
650	2	4	_aNANOTECHNOLOGY.
710	2		_aSpringerLink (Online service)
773	0		_tSpringer eBooks
776	0	8	_iPrinted edition: _z9781402050800
830		0	_aAdvanced Microelectronics, _x1437-0387 ; _v25
856	4	0	_uhttp://dx.doi.org/10.1007/1-4020-5081-X _zVer el texto completo en las instalaciones del CICY
912			_aZDB-2-ENG
942			_2ddc _cER
999			_c61129 _d61129