000			03518nam a22005055i 4500
001			978-1-4020-5546-1
003			DE-He213
005			20251006084522.0
007			cr nn 008mamaa
008			100301s2007 ne | s |||| 0|eng d
020			_a9781402055461
020			_a99781402055461
024	7		_a10.1007/978-1-4020-5546-1 _2doi
082	0	4	_a621.3815 _223
100	1		_aNedjah, Nadia. _eauthor.
245	1	0	_aCo-design for System Acceleration _h[electronic resource] : _bA Quantitative Approach / _cby Nadia Nedjah, Luiza De Macedo Mourelle.
264		1	_aDordrecht : _bSpringer Netherlands, _c2007.
300			_aXIX, 229 p. _bonline resource.
336			_atext _btxt _2rdacontent
337			_acomputer _bc _2rdamedia
338			_aonline resource _bcr _2rdacarrier
347			_atext file _bPDF _2rda
505	0		_aThe Co-design Methodology -- The Co-design System -- VHDL Model of the Co-design System -- Shared Memory Configuration -- Dual-port Memory Configuration -- Cache Memory Configuration -- Advanced Topics and Further Research.
520			_aIn Co-Design for System Acceleration, we are concerned with studying the co-design methodology, in general, and how to determine the more suitable interface mechanism in a co-design system, in particular. This will be based on the characteristics of the application and those of the target architecture of the system. We provide guidelines to support the designer's choice of the interface mechanism. The content of Co-Design for System Acceleration is divided into eight chapters. We present co-design as a methodology for the integrated design of systems implemented using both hardware and software components. This includes high-level synthesis and the new technologies available for its implementation. The physical co-design system is then presented. The development route adopted is discussed and the target architecture described. The relation between the execution times and the interface mechanisms is analyzed. In order to investigate the performance of the co-design system for different characteristics of the application and of the architecture, we developed a VHDL model of our co-design system. The timing characteristics of the system are introduced, that is times for parameter passing and bus arbitration for each interface mechanism, together with their handshake completion times. The relation between the coprocessor memory accesses and the interface mechanisms is then studied. Several memory configurations are presented and studied: single-port memory, dual-port memory and cache memory. We also introduce some new trends in co-design and system acceleration.
650		0	_aENGINEERING.
650		0	_aCOMPUTER HARDWARE.
650		0	_aMEMORY MANAGEMENT (COMPUTER SCIENCE).
650		0	_aCOMPUTER NETWORK ARCHITECTURES.
650		0	_aCOMPUTER SCIENCE.
650		0	_aSYSTEMS ENGINEERING.
650	1	4	_aENGINEERING.
650	2	4	_aCIRCUITS AND SYSTEMS.
650	2	4	_aCOMPUTER HARDWARE.
650	2	4	_aCOMPUTER SYSTEMS ORGANIZATION AND COMMUNICATION NETWORKS.
650	2	4	_aMEMORY STRUCTURES.
650	2	4	_aPROCESSOR ARCHITECTURES.
700	1		_aMourelle, Luiza De Macedo. _eauthor.
710	2		_aSpringerLink (Online service)
773	0		_tSpringer eBooks
776	0	8	_iPrinted edition: _z9781402055454
856	4	0	_uhttp://dx.doi.org/10.1007/978-1-4020-5546-1 _zVer el texto completo en las instalaciones del CICY
912			_aZDB-2-ENG
942			_2ddc _cER
999			_c61323 _d61323