000			03651nam a22005055i 4500
001			978-1-4020-5912-4
003			DE-He213
005			20251006084527.0
007			cr nn 008mamaa
008			130821s2007 ne | s |||| 0|eng d
020			_a9781402059124
020			_a99781402059124
024	7		_a10.1007/978-1-4020-5912-4 _2doi
082	0	4	_a621.3 _223
100	1		_aMuller, Paul. _eauthor.
245	1	0	_aCMOS Multichannel Single-Chip Receivers for Multi-Gigabit Optical Data Communications _h[electronic resource] / _cby Paul Muller, Yusuf Leblebici.
264		1	_aDordrecht : _bSpringer Netherlands : _bImprint: Springer, _c2007.
300			_bonline resource.
336			_atext _btxt _2rdacontent
337			_acomputer _bc _2rdamedia
338			_aonline resource _bcr _2rdacarrier
347			_atext file _bPDF _2rda
490	1		_aAnalog Circuits and Signal Processing, _x1872-082X
505	0		_aIntegrated Photonic Systems -- Basic Concepts -- System-Level Specifications -- Silicon Photodetectors -- Transimpedance Amplifier Design -- Limiting Amplifier Design -- Clock and Data Recovery Circuit.
520			_aWhile the throughput of microprocessor systems tends to increase as a result of ongoing technology scaling and the advent of multi-core systems, the off-chip I/O communication bandwidth emerges as one of the potential bottlenecks that limit overall performance. In order to alleviate the communication speed constraints, optical data communication interfaces move ever closer to the processor core. It is widely expected that future generation digital systems will increasingly rely on chip-to-chip and board-to-board optical data communications for higher bandwidth and better noise immunity. This book focuses on optical communications for short and very short distance applications and discusses the monolithic integration of optical receivers with processing elements in standard CMOS technologies. CMOS Multi-Channel Single-Chip Receivers for Multi-Gigabit Optical Data Communications provides the reader with the necessary background knowledge to fully understand the trade-offs in short-distance communication receiver design and presents the key issues to be addressed in the development of such receivers in CMOS technologies. Moreover, novel design approaches are presented. A system-level design methodology allows for the impact analysis of different block specifications and system-wide design optimization. Statistical models are used for design space exploration in the scope of jitter tolerance analysis of clock recovery circuits. CMOS Multi-Channel Single-Chip Receivers for Multi-Gigabit Optical Data Communications is required reading for practicing engineers and researchers in the field of short-distance optical communications and optical CMOS receiver design.
650		0	_aENGINEERING.
650		0	_aMICROWAVES.
650		0	_aELECTRONICS.
650		0	_aTELECOMMUNICATION.
650		0	_aSYSTEMS ENGINEERING.
650	1	4	_aENGINEERING.
650	2	4	_aMICROWAVES, RF AND OPTICAL ENGINEERING.
650	2	4	_aCIRCUITS AND SYSTEMS.
650	2	4	_aELECTRONICS AND MICROELECTRONICS, INSTRUMENTATION.
650	2	4	_aCOMMUNICATIONS ENGINEERING, NETWORKS.
700	1		_aLeblebici, Yusuf. _eauthor.
710	2		_aSpringerLink (Online service)
773	0		_tSpringer eBooks
776	0	8	_iPrinted edition: _z9781402059117
830		0	_aAnalog Circuits and Signal Processing, _x1872-082X
856	4	0	_uhttp://dx.doi.org/10.1007/978-1-4020-5912-4 _zVer el texto completo en las instalaciones del CICY
912			_aZDB-2-ENG
942			_2ddc _cER
999			_c61489 _d61489