000			04150nam a22005055i 4500
001			978-1-4020-5928-5
003			DE-He213
005			20251006084527.0
007			cr nn 008mamaa
008			100301s2007 ne | s |||| 0|eng d
020			_a9781402059285
020			_a99781402059285
024	7		_a10.1007/978-1-4020-5928-5 _2doi
082	0	4	_a621.3 _223
100	1		_aBourdi, Taoufik. _eauthor.
245	1	0	_aCMOS Single Chip Fast Frequency Hopping Synthesizers For Wireless Multi-Gigahertz Applications _h[electronic resource] : _bDesign Methodology, Analysis, and Implementation / _cby Taoufik Bourdi, Izzet Kale.
264		1	_aDordrecht : _bSpringer Netherlands, _c2007.
300			_aXII, 208 p. _bonline resource.
336			_atext _btxt _2rdacontent
337			_acomputer _bc _2rdamedia
338			_aonline resource _bcr _2rdacarrier
347			_atext file _bPDF _2rda
490	1		_aAnalog Circuits and Signal Processing
505	0		_aWireless Communication Systems -- Phase-Locked Loop Frequency Synthesizers -- System Simulation of ?-?-Based Fractional-N Synthesizers -- Multimode ?-?-Based Fractional-N Frequency Synthesizer -- Improved Performance Fractional-N Frequency Synthesizer -- Conclusion And Further Work.
520			_aRecently, wireless LAN standards have emerged in the market. Those standards operate in various frequency ranges. To reduce component count, it is of importance to design a multi-mode frequency synthesizer that serves all wireless LAN standards including 802.11a, 802.11b and 802.11g standards. With different specifications for those standards, designing integer-based phase-locked loop frequency synthesizers can not be achieved. Fractional-N frequency synthesizers offer the solution required for a common multi-mode local oscillator. Those fractional-N synthesizers are based on delta-sigma modulators which in combination with a divider yield the fractional division required for the desired frequency of interest. In CMOS Single Chip Fast Frequency Hopping Synthesizers for Wireless Multi-Gigahertz Applications, the authors outline detailed design methodology for fast frequency hopping synthesizers for RF and wireless communications applications. Great emphasis on fractional-N delta-sigma based phase locked loops from specifications, system analysis and architecture planning to circuit design and silicon implementation. The book describes an efficient design and characterization methodology that has been developed to study loop trade-offs in both open and close loop modelling techniques. This is based on a simulation platform that incorporates both behavioral models and measured/simulated sub-blocks of the chosen frequency synthesizer. The platform predicts accurately the phase noise, spurious and switching performance of the final design. Therefore excellent phase noise and spurious performance can be achieved while meeting all the specified requirements. The design methodology reduces the need for silicon re-spin enabling circuit designers to directly meet cost, performance and schedule milestones. The developed knowledge and techniques have been used in the successful design and implementation of two high speed multi-mode fractional-N frequency synthesizers for the IEEE 801.11a/b/g standards. Both synthesizer designs are described in details.
650		0	_aENGINEERING.
650		0	_aMICROWAVES.
650		0	_aELECTRONICS.
650		0	_aTELECOMMUNICATION.
650		0	_aSYSTEMS ENGINEERING.
650	1	4	_aENGINEERING.
650	2	4	_aMICROWAVES, RF AND OPTICAL ENGINEERING.
650	2	4	_aCIRCUITS AND SYSTEMS.
650	2	4	_aELECTRONICS AND MICROELECTRONICS, INSTRUMENTATION.
650	2	4	_aCOMMUNICATIONS ENGINEERING, NETWORKS.
700	1		_aKale, Izzet. _eauthor.
710	2		_aSpringerLink (Online service)
773	0		_tSpringer eBooks
776	0	8	_iPrinted edition: _z9781402059278
830		0	_aAnalog Circuits and Signal Processing
856	4	0	_uhttp://dx.doi.org/10.1007/978-1-4020-5928-5 _zVer el texto completo en las instalaciones del CICY
912			_aZDB-2-ENG
942			_2ddc _cER
999			_c61496 _d61496