Leakage in Nanometer CMOS Technologies [recurso electrónico] / by Siva G. Narendra, Anantha Chandrakasan.

Taxonomy of Leakage: Sources, Impact, and Solutions -- Leakage Dependence on Input Vector -- Power Gating and Dynamic Voltage Scaling -- Methodologies for Power Gating -- Body Biasing -- Process Variation and Adaptive Design -- Memory Leakage Reduction -- Active Leakage Reduction and Multi-Performance Devices -- Impact of Leakage Power and Variation on Testing -- Case Study: Leakage Reduction in Hitachi/Renesas Microprocessors -- Case Study: Leakage Reduction in the Intel Xscale Microprocessor -- Transistor Design to Reduce Leakage.

The goal of Leakage in Nanometer CMOS Technologies is to provide ample detail so that the reader can understand why leakage power components are becoming increasingly relevant in CMOS systems that use nanometer scale MOS devices. Leakage current sources at the MOS device level including sub-threshold and different types of tunneling are discussed in detail. The book covers promising solutions at the device, circuit, and architecture levels of abstraction. Manifestation of these MOS device leakage components at the full chip level depends considerably on several aspects including the nature of the circuit block, its state, its application workload, and Process/Voltage/Temperature conditions. The sensitivity of the various MOS leakage sources to these conditions are described from the first principles. The resulting manifestations are discussed at length to help the reader understand the effectiveness of leakage power reduction solutions under these different conditions. Case studies are presented to highlight real world examples that reap the benefits of leakage power reduction solutions. Finally, the book highlights different device design choices that exist to mitigate increases in the leakage components as technology scales.